The present invention relates to a field effect transistor, and more particularly, to a field effect transistor having a channel length on the order of a submicron order.
It is known that when the channel length of a field effect transistor is on the order of a submicron or less, the short channel effect effect the threshold voltage towards zero and, as a result, increases the drain current (leakage current) when the transistor is in the cutoff condition.
In order to avoid the short channel effect, there is proposed a field effect transistor having a channel unevenly doped as shown in FIG. 9. The field effect transistor is constructed so that a gate insulating film 114 and a gate electrode 118 are formed on a surface of a p-type silicon substrate (or well region) 110, and then tilt-angle rotational ion implantation (.alpha.: tilt-angle of implantation) is effected with the gate electrode 118 used as a mask to form p-type heavily doped regions 116 under about one third of the gate electrode width from both edges of the gate electrode 118. Ions are further implanted into surface portions of the silicon substrate 110 approximately perpendicularly to the surface to form n-type lightly doped regions 121 and 122 on both sides of the gate electrode 118. Subsequently, SiO.sub.2 side walls 123 and 124 are provided on both sides of the gate electrode 118, and then ions are implanted into surface portions of the silicon substrate 110 approximately perpendicularly to the surface to form n-type heavily doped regions 119 and 120. The n-type lightly doped region 121 and the n-type heavily doped region 119 constitute a source region S, while the n-type lightly doped region 122 and the n-type heavily doped region 120 constitute a drain region D (LDD (Lightly Doped Drain) structure). In the field effect transistor, the p-type heavily doped regions (channel diffusion regions) 116 are provided at both ends of a channel region 117. Therefore, the possible widening of a depletion layer may be suppressed at the boundaries of the source region S and the drain region D to allow the short channel effect to be suppressed.
However, in the above-mentioned conventional field effect transistor, the width the depletion layer is limited by the p-type heavily doped region 116. As a result an endurance voltage at the junction between the drain region D and the silicon substrate 110 is reduced. Furthermore, the junction capacitance between the drain region D and the silicon substrate 110 increases which reduces the response speed of the transistor and reduces the trigger current causing latch-up as shown in FIGS. 12A and 12B.
To suppress the increase of the junction capacitance between the drain region and the silicon substrate, a field effect transistor such as shown in FIG. 10A may be constructed including a semiconductor substrate 131 of a conductivity type (p- or n-type), a gate insulating film 132 and a gate electrode 133 formed on the substrate 131, source and drain regions composed of diffusion layers 134, 135 of opposite conductivity type (n- or p-type) arranged in contact with edge portions of the gate insulating film 132, and a diffusion layer 137 of the same conductivity type as the semiconductor substrate 131 is arranged in contact with the source and drain regions and apart from a channel region with an impurity concentration greater than the impurity concentration of the semiconductor substrate 131. Since the above transistor does not have a heavily doped region at either side of the channel region, the widening of the depletion layer is not suppressed at the boundaries of the drain region and the source region which results in losing control of the short channel effect.
If the lightly doped diffusion layer 137 expands to a portion beneath the channel region, the impurity concentration in the gate is reduced which results in losing control of the short channel effect. In order to prevent the above-mentioned phenomenon, the channel region and the lightly doped diffusion layer 137 are separated from each other in the above transistor.
In order to obtain the above-mentioned separated structure, the lightly doped diffusion region 137 is formed during a side wall formation process, or otherwise a photoresist is required as a mask to achieve the intended distance from the channel region. Therefore, the process is complicated. In the latter case in particular, a self-aligning arrangement not having the benefit of the gate electrode including a side wall 138 used as a mask is difficult to achieve with a margin of error on the submicron order. Also, in the above transistor, the short channel effect occurs when the channel length is on the order of a submicron as shown in FIG. 11.
Another problem is the lightly doped diffusion region 137 and the channel region must be separated apart from each other in order to prevent the lightly doped diffusion region 137 from expanding into the channel region. In order to obtain the above-mentioned separated structure, the side wall formation process is executed two times to separate the lightly doped diffusion region from the channel region, or a photoresist is provided as a mask to result in the disadvantages of complicated process and reduced process margin.